(1) Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device and, more particularly, to a method of fabricating a storage capacitor in a stacked type of a dynamic random-access memory (hereinafter referred to as "DRAM").
(2) Description of the Related Art
Conventionally, in many cases, DRAM adopts a memory cell composed of one transistor serving as a switch and one storage capacitor. The DRAM designed in such a structure includes a stacked type memory cell.
FIGS. 1A to 1E are sectional views for explaining the method of fabricating the conventional stacked type memory cell in the order of its fabricating steps.
First, as seen from FIG. 1A, formed on a silicon substrate 1 are a field oxide film 2, a gate insulating film 3, gate electrodes 4, source/drain regions 5 and first insulating films 6 covering the gate electrodes 4.
As seen from FIG. 1B, a second insulating film 7 is formed on the entire outer (upper) surface using chemical vapor deposition (CVD) techniques (hereinafter simply referred to as "CVD"), and thereafter a contact hole 8 is opened at the position corresponding to a storage capacitor by photolithography and reactive ion-etching (RIE) techniques (hereinafter simply referred to as "RIE").
As seen from FIG. 1C, a polysilicon (also called polycrystalline silicon) film is formed by the CVD, and further a capacitor storage electrode 20 of the polysilicon film is formed by the RIE using a photoresist film 9 as a mask.
As seen from FIG. 1D, a dielectric film 12 is formed on the resultant surface, and subsequently a capacitor opposing electrode 13 of a polysilicon film is formed. The capacitor opposing electrode 13 is formed so as to cover the capacitor storage electrode 20, and the dielectric film 12 is etched using the capacitor opposing electrode 13 as a mask.
Finally, as seen from FIG. 1E, a third insulating film 14 serving as an inter-layer insulating film is formed by the CVD, and thereafter the third insulating film 14 and the second insulating film 7 on the source/drain region 5 are selectively removed to open a contact hole for a bit followed by the formation of a metal wiring 15.
The above conventional stacked type memory cell has the following defects. For the storage capacitor to have a large capacitance, the level difference in the gate electrodes 4 is used to increase the surface area of the capacitor storage electrode 20. Further, the thickness of the polysilicon film of the capacitor storage electrode 20 is made as thin as possible in order to facilitate easy etching on the portion having the level difference. For example, the polysilicon film having the thickness in the order of 200 nm was used at an early stage. However, if the capacitor storage electrode 20 is thin, its side area counts small in terms of an increase in the surface area.
As the memory cell area is made smaller, the pattern of the capacitor storage electrode 20 must be made smaller. Therefore, it is not possible to secure a sufficient area for the capacitor if only the surface of the capacitor storage electrode 20 is used in such a structure.